CXMT's fifth-generation DRAM is in mass production — more dies per wafer, not an HBM fairy tale
Reuters reported on September 20 that CXMT's fifth-generation DRAM platform had entered mass production, with feature spacing claimed at 11.95 nanometres and at least 50% more gross dies per wafer than the prior generation. Two 24-gigabit LPDDR5X parts are already in production. Gross dies are not finished-test yield, and the "on par" line is an executive quote.
What happened
On September 20, 2026, Reuters reported that ChangXin Memory Technologies, China’s leading maker and a 2026 Shanghai STAR Market listee, said its fifth-generation technology platform had entered mass production. Che Pan and Eduardo Baptista framed the claim as a possible step toward stronger competition with , , and on mainstream memory. They did not present it as an audited process win.
CXMT said the new platform packs storage structures closer together, so more memory fits on each chip and more chips come off each wafer. The company put key feature spacing in the data-storage region at 11.95 nanometres, using quadruple patterning, which repeats patterning steps to print finer lines. Luo Xiaodong, CXMT’s vice president and marketing-centre head, told the 2026 World Manufacturing Convention in Hefei that process capability was “now on par with the most advanced mass-produced nodes out there in the industry.” That is an executive quote. It is not a third-party process review.
The product points in the Reuters piece are concrete. Two 24-gigabit LPDDR5X parts, each holding 50% more data than CXMT’s previous equivalent products, are already in mass production, in two formats for smartphones and portable devices. On wafer economics, CXMT said the platform can produce at least 50% more gross dies per wafer than its fourth-generation platform, using an 8-gigabit chip as the baseline. Reuters notes that gross dies count potential chips before defective units are excluded. That is not a finished-test yield percentage.
CXMT said the platform was developed with computer simulations and joint work with Chinese chip-equipment makers on critical steps. The wire’s background is Beijing’s push to rely less on foreign semiconductor tools, and U.S. export controls since 2022 that limit some of that equipment. That is context, not a new policy story.
This is a commodity DRAM step, LPDDR5X for phones and PCs. It is a different chapter from CXMT’s early work, where trial yields have been reported around 25% and stacking is the hard part. The two stories stay in different kitchens.
Why it matters
Memory is where China’s AI silicon story either gets cheaper or stays expensive. , , and every domestic accelerator still drink high-bandwidth memory that Korea and Micron dominate. A Gen-5 commodity ramp can matter on mobile and server DRAM, give buyers another source, and free some Korean wafer starts for HBM. It does not mean Chinese HBM just caught up.
The usable facts are a claimed mass-production DRAM platform, a claimed gross-die lift of at least 50% versus Gen-4 on an 8-gigabit baseline, and 24-gigabit LPDDR5X already in production. The stretch to avoid is treating Luo’s “on par” line as verified process parity, or treating gross dies as chips you can sell. Independent process writeups and customer teardowns are still missing.
What to watch is a third-party check of the 11.95-nanometre claim, phone makers naming CXMT LPDDR5X in a teardown, and whether CXMT’s separate HBM trial yields move off that early band. Until then this is a company claim about a real product class, with the die count kept cautious.
The HBM chapter is CXMT’s small-batch HBM3E. The Korean yield story beside it is Samsung HBM4 near 80%.