TSMC's 3nm, 2nm, and CoWoS stay tight as AWS and MediaTek reshuffle the queue
DigiTimes reported from Hsinchu on September 15 that TSMC's 3nm, 2nm, and CoWoS capacity was still short, and that customer changes were reshuffling allocation. Annapurna, MediaTek's Google TPU work, and a TPU v9 split between CoWoS-L and Intel EMIB-T stay reportedly. The full English article was paywalled.
What happened
DigiTimes (Monica Chen, Hsinchu, September 15, 2026) reported that TSMC’s 3nm, 2nm, and capacity remained in short supply late in the third quarter of 2026, as major customer orders and the pairing of front-end wafers with back-end packaging shifted. The English page’s visible opening matches that frame. The full English body was paywalled. The customer details below are paraphrased from DigiTimes’ Chinese report of the same piece and from secondary writeups of it. Treat them as supply-chain sourcing and keep reportedly on every name.
Reportedly, and Apple still hold large shares of advanced process and packaging. Amazon Web Services’ Annapurna team has increased AI-chip wafer starts, securing more 3nm capacity and a higher place in the related CoWoS line. MediaTek, beyond phone chips, is competing for 2nm, 3nm, and CoWoS-S and CoWoS-L capacity on Google TPU orders.
The queue change that makes the note worth reading is the split. After MediaTek took on large Google TPU work, the next TPU, called v9 in that reporting, is expected to use both TSMC CoWoS-L and EMIB-T. DigiTimes’ supply-chain sources say that dual back end prompted TSMC to fine-tune MediaTek’s 3nm and 2nm arrangements, rather than treat the flow like a customer that takes TSMC from wafer to package. At the same time, Annapurna’s larger 3nm and CoWoS ask reportedly moved up the priority stack.
Capacity figures circulating with the same story come from secondary digests, not from a TSMC filing. They describe 2nm capacity at Hsinchu’s Baoshan Fab 20 and Kaohsiung’s Fab 22 aimed near 100,000 wafers a month combined by the end of October, 3nm in Tainan near 185,000 wafers a month by then, and overall utilization in the mid-90s, with leading nodes full. CoWoS shortage is said to push overflow to ASE Group’s SPIL first, then Amkor and others, with some assembly visibility talked out to 2028. Those numbers stay reported estimates.
This is the twin of the Kaohsiung Mini-Loop story. That one is tool-validation infrastructure. This one is who gets the scarce slots while the infrastructure catches up.
Why it matters
Late-quarter allocation notes are how chip buyers see next year’s pain early. When AWS raises Annapurna’s priority and Google’s TPU packaging splits across TSMC and Intel, TSMC’s job becomes portfolio math, not one line everyone waits in. CoWoS stays one choke. Front-end 3nm and 2nm tightness is the other.
In these supply-chain tellings, Nvidia is still the gravitational 3nm customer, Apple remains central to the 2nm demand story, and custom silicon from AWS and Google is no longer a rounding error. This is not capacity. It is Hsinchu gossip with global cloud names attached.
What to watch is whether the reshuffle shows up in company comments or in a second wire with named sources, how a CoWoS-L versus EMIB-T split on TPU v9 changes MediaTek’s foundry mix, and whether Annapurna partners named only in secondary digests, including Alchip, Marvell, and Qualcomm, keep asking for more wafers. Until the full English DigiTimes piece can be read end to end, the soft capacity figures stay reportedly.
The tool-homework version of the same bottleneck is TSMC’s Kaohsiung Mini-Loop.