China’s top chip factory tries the same power trick Intel and TSMC already use

What happened

TrendForce’s September 17 note is easy to skim past if you only want GPU names. It should not be. Industry sources, as TrendForce tells it, say AMEC and Naura are working with SMIC on backside power delivery for SMIC N7 and N5 work, and AMEC’s atomic layer deposition tool has reportedly cleared SMIC validation. Backside power routes power up from the rear of the die so the front-side wiring can carry signals more cleanly. Intel branded its version PowerVia. TSMC’s Super Power Rail path points at the same class of idea on leading nodes. China does not get a free skip of that physics homework just because export rules blocked some lithography.

Why this belongs next to an Ascend week: when you cannot lean on EUV the way TSMC can, you hunt every packaging and power-delivery trick that stretches DUV-era tools. SMIC’s public node branding (N7/N5-class) already lives in a contested translation layer versus Western node names. Backside power does not settle that naming fight. It does show the domestic equipment stack trying to show up where process complexity used to mean “import the tool or stop.” AMEC clearing a validation gate, if the TrendForce sourcing holds, is an equipment-localization mile marker even before happy yield stories arrive.

If you follow this from outside China, keep the humility clause in the same paragraph as the excitement. Validation is not high-volume manufacturing. A tool clearing a test does not mean every SMIC AI-related wafer tomorrow uses backside power. Some of the underlying reporting chain may lean on Korean or trade-press industry sources that deserve a primary URL before any CLEAR. Until that primary is nailed, Brief language stays “reportedly” and “industry sources say.”

Why it matters

Compared with Intel and TSMC, SMIC is early. Those firms already market backside-power generations as part of a roadmap customers can buy into. SMIC’s signal is that Chinese fabs and tool vendors are practicing the same playbook under tighter constraints. Pair it with CXMT’s HBM yield struggle and Huawei’s capacity confession, and the pattern is consistent: China is building the hard supporting cast for AI silicon, and the supporting cast is still in rehearsal.

What to watch is formal SMIC technical talk, more named tool qualifications from AMEC and Naura, and any product silicon described as using backside power in volume. Watch whether this stays an Etcetera process nugget or becomes a lead when a customer chip is proven. For now it is the quiet fab subplot behind louder Ascend headlines: not a GPU, still part of whether those GPUs get faster without a magic EUV machine.